Emerging Era of Heterogeneous Integration For System Chips: Technology and Business Solutions

April 30, 2006
Both trends in the technology development and business models of the IC industry undergo significant changes as it enters the 21st century. As both circuits techniques and process technologies advanced rapidly through the late 1990s, ICs with various functions, specialized for digital, analog, memory or radio frequency (RF) functions, were developed to further reduce the cost and size of ES, as well as to diversify their applications. The long standing demand for a portable networking ES has driven the emergency of mobile-intelligence applications (MIA), such as personal digital assistants (PDAs), portable audio/video devices, digital cameras and cellular phones, etc. These MIAs were built as vertically integrated closed systems with an additional constraint that they be of a limited size (that is, with volume measured in cm3), but the system complexity is dramatically increasing along with the end user's desire for complete 5C (computer, communication, consumer, control, and content) functionally through a single MIA. The pressure to drive down both cost and size while increasing the functionality embedded in MIAs, requires most subsystem functions to implemented in ICs. These ICs need to merge digital, analog, memory, RF and power-related IC five families, as much as possible into a smaller packaging form factor. An era of system chips (SC) is thus emerging! It is believed that once the technology has matured, system chips will also be used for general applications.

One trend being followed is to design a system-on-a-chip (SOC), which includes all or parts of five families on a single die. Another alternative, known as system in package (SiP), is to assemble different IC family dies horizontally on the same substrate within a package. Meanwhile, a new technology permitting the stacking of multiple dies in a small chip-scale package (MCSP) is emerging, which allows the third-dimension to be used to achieve more function or density in a given footprint area. One example of a stacked CSP is a memory combo that can include six layers of memory dies in a ball grid-array (BGA) package. Besides conventional wire bonding, flip-chip techniques using solder bumps and interposers are being adopted increasingly.

A key challenge to the prosperity of the future IC industry is how to effectively assemble multiple functions into a limited form factor with justifiable cost controls while being able to optimize performance of individual IC families. However, a study of central processing units (CPUs) of digital, analog, memory and RF circuits revealed that they exhibit quite different behaviors as technology is scaled. Combining different families on a die with a combined technology base may not permit an optimized solution. With the rapid development of SOC, SiP, Product-in-package (PiP), package-on-package (PoP) and stacked CSP technologies, it is envisioned that the most powerful system chip in the coming years should incorporate an integrated structure using multiple dies with heterogeneous technologies and voltage operations, which fully utilize the multi-dimensional space within a CSP package. An example would include separately connected building blocks, including a stack of memory dies, an analog die overlaid on either a SOC or digital die, and an independent RF die located on top of a multi-layer interconnected substrate inside a package, each with different control and I/O paths.

In addition, control software would be coded into the non-volatile memory (NVM) in the memory stack. Making an appearance on the IC technology horizon is a new technology known as multi-dimensional die-integration system chips (MDSCs)! The architecture of MDSCs can be conceptualized as a metropolitan-city-like die society cluster, structured similarly to modern high-rise buildings such as New York or Taipei!

Although implementing an MIA has brought back VI, the required business model is different from that of the mainframe period, due to more significant interactive modes among the four ES segments - cannel/ application, system architecture, software and hardware/ICs. The new VI system should not be viewed as a closed system, but should be developed as an integrated circle with direct interactions between any two segments, even between the application layer at the top and the IC layer at the bottom, thereby allowing faster SC product introduction. Due to horizontal segmentation in the 1990s, however, not many companies today are capable of developing and owning technologies in all four segments. Instead, each segment has several successful specialty companies. A clustered integration structure allows various companies with complementary skills from different specialty segments to either form alliances or partnerships to realize effective vertical integration of knowledge. To shorten the IC design-win circle, companies in a cluster need to engage each other early on to co-define specifications and to begin co-development sooner. Organizing a cluster of companies together to achieve effective vertical integration is termed clustered virtual-vertical integration (CVVI).

Both ES and IC industries are undergoing major paradigm shifts. The emergency of HI is transforming both, especially the IC industry by four aspects: (1) synergistic growth of technologies; (2) different business structures; (3) growing emphasis on knowledge economy; and (4) mix-and-match in human culture and IC usages.

Note: The above article is excerpted from Dr. Nicky Lu's articles published by the FSA Forum in 2005.




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