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Press Releases
 
Etron Enables a World of Miniaturized IOT Wearable Devices with Revolutionary New DRAM–RPC DRAM
December 20, 2018
 
FOR IMMEDIATE RELEASE
[NEWS RELEASE]


Etron Enables a World of Miniaturized IOT Wearable Devices with Revolutionary New DRAM–RPC DRAM

The next generation of consumer electronic gadgets will feature a growing number of wearable devices, many including video capture and/or playback functions. Video is notorious for consuming bandwidth and storage while wearable platforms impose hard constraints on physical size of the electronic components & associated interconnect. Taken together, these constraints create additional challenges on system designers.

Etron has developed new DRAM architecture - RPC DRAMTM- featuring x16 DDR3 - LPDDR3 bandwidth but using only 22 switching signals in a 40 ball FI-WLCSP Package. The 256 Mbit DRAM is 2 x 4.4 mm. All 40 balls fit within the perimeter of the die using an industry standard 400 micron ball pitch making it the ideal memory for use in many wearable video-enabled IOT devices.

Benefits from using the new Etron DRAM are found on the system ASIC too. A PHY used with the new Etron DRAM has 22 switching signals out of a total of 40 PHY bonding pads. The same bandwidth in a DDR3 PHY requires 47 switching signals (x16 data bus) and a total of ~100 bonding pads. The new Etron DRAM uses less than half the bonding pads on the system ASIC for the memory interface vs DDR3 of the same bandwidth.

Buffer memory is commonly found in video systems. Example applications include video rate conversion, display buffering, lens dewarping & shading correction, slow-motion buffering etc. Common applications require the storage of only one or two video frames (ie video rate conversion and display buffering) while in other applications such as slow-motion video buffering there isn’t a hard limit.

One area where hard limits are commonly encountered is the physical size of the electronics in wearable devices. For example, in an eyeglass form-factor video capture/playback system, DDR3 bandwidth is sufficient for a display buffer but the large 9 x 13 mm BGA won’t fit in the allotted space.

DDR3 memory is offered in an x16 configuration in a 96 ball BGA package that is approximately 9 x 13 mm. No matter what die capacity is used, the minimum package size remains the same, being set by the standardized ball footprint of six columns of 16 balls using a 0.8 mm pitch. Within a wide range of die capacities (256 Mbit to 8 Gbit) the same BGA package is used.

Fan-In Wafer Level CSP (“FI-WLCSP”) packages are manufactured differently than BGAs. Instead of assembling one package at a time an entire wafer is packaged in a batch. Each packaged unit is the size of the semiconductor die: A small die results in a small FI-WLCSP package.

No substrate is used and there are no wirebonding or flip-chip assembly steps. Package assembly consists of additive steps comprising deposited dielectrics and conductors that are photo-defined followed by electroplating and solder ball drop. All processing is done on full wafers.

Because all solder balls must fit within the perimeter of the semiconductor die, it is difficult to make high lead count packages using small die. For that reason, lower capacity DRAMs are generally not produced in FI-WLCSP packages: the ball pitch would be too small to be manufactured. On the other hand, a large DRAM die may support a manufactured ball pitch but the total silicon size is too large to withstand strain from thermal cycling: the silicon and PCB have too large of a mismatch of thermal expansion coefficients.

Depending on the design of the system ASIC, a hypothetical pad-limited edge-bonded die with 240 leads has 60 bonding pads per side and 100 total pads reserved for the DDR3 interface. Substituting the PRC DRAMTM PHY saves a total of 60 bonding pads total or 15 per side. Comparing the two memory interface options implemented on hypothetical pad-limited ASICs shows the ASIC designed to use the Etron DRAM to be significantly smaller 56.25%.

Etron’s Revolutionary New DRAM–RPC DRAMTM will be featured at CES 2019 (Jan 8-11). Please meet Etron at booth No. 21615, South Hall 1, Las Vegas Convention Center. For further information please visit www.etron.com.

About Etron Technology, Inc
Etron Technology, Inc. (Taiwan GTSM: 5351) is a world-class fabless IC design and product company specializing in application-driven memories, smart ICs and 3D heterogeneous Integration designs of multiple dices primarily adding values for product differentiation of system customers, which include CE- & IOT-DRAMs, Know-Good-Die Memories, High-Speed USB Type-C Controller Chipsets, Novel 3D Natural-Light Depth-Map Vision Sensing ICs and Platforms and the smallest and lightest Spherical 360° video capturing chips and subsystems.

For further information, please contact:
Ms. Justine Tsai
Tel: +1-929-519-8724
Email: pr@etron.com.tw